Field
In one aspect, the following relates to pipelined processing of requests, and in one particular aspect, to a pipeline for accessing ECC protected memory, such as a cache.
Related Art
Although semiconductor memories are generally reliable, potential errors in caches, such as soft errors, have become an increasing concern as geometries of transistors implementing bit cells of caches continue to shrink. As transistor geometries continue to shrink, an amount of energy required to change a value of a particular bit continues to decrease as well. Therefore, error detection and error correction have become increasingly important capabilities of memories, such as caches and as well as Dynamic Random Access Memory (DRAM). Providing error detection or error detection and correction comes at some cost, which in general is related to a capability of the technique employed to detect and correct different kinds of errors. Typically, some form of processing is applied to a set of bits over which error detection and/or error detection and correction is desired. Such processing typically results in one or more additional bits that are associated with the set of bits. Techniques that support a capability to detect and correct at least one-bit errors are often called Error Correcting Codes (ECC), while a code that simply detects but cannot correct an error is typically called an Error Detection Code. For example, a parity bit can be used to detect but not correct a one bit error in a set of bits. For example, a common Hamming code can be applied to a set of bits and a result of that application are bits that can be used to detect and correct one bit errors and detect, but not correct, two-bit errors. Using ECC on cache data increases an amount of processing required in order to read the caches.